Miniature passive electronic circuit components are conventionally fabricated in an array on a substrate. Exemplary types of passive electronic components of interest with regard to the present invention are resistors and capacitors. FIGS. 1A and 1B show an array of resistors in which a substrate 10 includes a first (or upper) major surface 14 and a second (or lower) major surface 16 carrying, respectively, first spaced-apart segmented electrical conductor lines 18 and second spaced-apart segmented electrical conductor lines 20 (end portions of which shown in dashed lines in FIG. 1B). Segmented conductor lines 18 are in parallel alignment, and segmented conductor lines 20 are in parallel alignment.
Each segmented conductor line 18 is composed of multiple electrode pads 22, adjacent ones of which are separated from each other by a small distance 24 and all of which are aligned along first major surface 14. Except for the two terminal end segmented conductor lines 18, each segmented conductor line 18 is positioned between two neighboring segmented conductor lines 18 and is separated from one of them by a relatively wide space 26 and from the other of them by a relatively narrow space or street 28u. Similarly, each segmented conductor line 20 is composed of multiple electrode pads 30, adjacent ones of which are separated from each other by a small distance 24 and all of which are aligned along second major surface 16. Except for the two terminal end segmented conductor lines 20, each segmented conductor line 20 is positioned between two neighboring segmented conductor lines 20 and is separated from one of them by a relatively wide space 26 and from the other one of them by a street 281.
The electrical conductor lines are also arranged in spatially aligned pairs of one electrical conductor line 18 on first major surface 14 and one electrical conductor line 20 on second major surface 16. First major surface 14 further includes multiple regions of resistive material 32 positioned in spaces 26 between electrode pads 22 of adjacent electrical conductor lines 18, as shown in FIGS. 1A and 1B. Second major surface 16 may also include regions of resistive material 32 in spaces 26 between adjacent electrode pads 30 of electrical conductor lines 20, which regions 32 are not shown in the drawing figures.
FIGS. 2 and 4 show a substrate of dielectric material 34 that is used in the fabrication of capacitors. Substrate 34 includes a first (or upper) major surface 36 and a second (or lower) major surface 38 between which multiple spaced-apart sheet electrodes 40 are internally stacked in plane parallel arrangement. FIG. 4 shows exposed side margins 42 of internal electrodes 40. There is no electrical conductor line formed on either of major surfaces 36 and 38.
Substrates 10 and 34 are cut, sometimes called diced, to singulate the passive electronic components. FIGS. 3A and 3B show first and second major surfaces 14 and 16, respectively, of substrate 10 after it has been broken apart to form multiple rowbars 48 of resistors. Rowbars 48 are then cut into separate chip resistors 52 (shown in FIG. 5). Capacitors 54 (shown in FIG. 6) are formed by dicing substrate 34 without formation of rowbars. Each chip resistor 52 includes an electrically conductive interconnect 56 that extends between electrical conductor lines 18 and 20 in each spatially aligned pair of them. Capacitor 54 includes an electrically conductive interconnect 58 that bridges across side margins 42 of internal electrodes 40. Conductive interconnects 56 are formed by applying a metal coating (e.g., a silver paste) to a side margin portion 60 of resistor substrate 10. Great precision is needed when forming conductive interconnects 56 and 58 to ensure that none of the metal coating extends across a region of resistive material 32 or connects both conductive interconnects 58 across first or second major surfaces 36 and 38, and thereby forms an electrically conductive bridge that would cause the resulting chip resistor 52 or capacitor 54 to become a short circuit.
Most prior art methods of forming conductive interconnects 56 between spatially aligned pairs of electrical conductor lines 18 and 20 entail applying a resist coating that covers and protects regions of resistive material 32 defined by spaces 26 between electrode pads 22 on major surface 14 while the metal coating is applied. However, recent technological advancements in component miniaturization have resulted in the formation of chip resistors 52 having respective length and width dimensions of about 0.6 mm×0.3 mm (0201 chip resistors) and a thickness of between about 90 microns and about 150 microns, as compared to prior art 0402 chip resistors having respective length and width dimensions of about 1.0 mm×0.5 mm. The small sizes of chip resistors 52 make accurate and efficient application of the resist coating exceedingly difficult to achieve. Consequently, chip manufacturers have begun to form conductive interconnects 56 on rowbars 48 rather than on discrete chip resistors 52 because rowbars 48 are significantly larger in size (typically having respective length and width dimensions of between about 36 mm and about 80 mm and between about 3.2 mm and about 0.6 mm) and are thus easier to handle during processing.
One prior art method of forming conductive interconnects 56 on chip resistors 52 entails cutting substrate 10 into multiple rowbars 48 and then dipping side margins 60 of each rowbar 48 into the metal coating. However, accurate application of the metal coating by dipping becomes virtually impossible as the size of rowbar 48 and chip resistor 52 decreases. Consequently, the metal coating bridges regions of resistive material 32 and causes the resulting chip resistor 52 to become a short circuit.
A second prior art method of forming conductive interconnects 56 on chip resistors 52, described in U.S. Pat. No. 5,753,299 to Garcia et al., entails screen printing the resist coating onto rowbars 48 so that the resist coating covers only selected regions of resistive material 32. The resist material-coated rowbars 48 are then sputter-coated with the metal coating to form conductive interconnects 56. Lastly, the resist coating is removed from rowbars 48 to expose regions of resistive material 32, and rowbar 48 is cut to form multiple individual chip resistors 52. Screen printing is a mechanical process and thus has inherent size limitations that have been reached. Specifically, screen printing is becoming ineffective to form next-generation, miniature chip resistors because this method cannot provide sufficient electrical conductor line straightness or accuracy. Further, screen printing results in the formation of nonuniform lines, and the resulting ragged edges predominate in the next-generation, miniature chip resistors.
A third prior art method of forming conductive interconnects 56 entails assembling numerous rowbars 48 face-to-face in a tight stack to form a fixture that is then sprayed with the metal coating. The uppermost and lowermost (terminal) rowbars 48 in the fixture are sacrificed because regions of resistive material 32 on these terminal rowbars 48 are oversprayed with the metal coating. Conductive interconnects 56 are, however, formed on the other stacked rowbars 48. Lastly, each rowbar 48 is cut to form multiple chip resistors 52.
Regarding terminating the ends of capacitors, conventional termination systems terminate the ends when they are in singulated, discrete capacitor form. More specifically, the most common prior art method of forming conductive interconnect 58 on unterminated capacitors entails holding a discrete, unterminated capacitor by its end and dipping it into a viscous termination paste. Once the paste has dried, the discrete, partly terminated capacitor is repositioned for dipping the opposite end into the viscous termination paste. Accurate application of the termination paste by dipping becomes virtually impossible as the sizes of capacitors 54 decrease. Consequently, a metal coating bridging both conductive interconnects 58 would cause the resulting nominal capacitor 54 to become a short circuit.
Because they are approaching their physical limits, all of the prior art methods are inadequate for accurately terminating the ends of next-generation, miniature passive electronic components, including chip resistors and capacitors. Consequently, a need has arisen for a highly efficient and accurate method of terminating next-generation, miniature passive electronic components.